1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to semiconductor memory devices including redundant memory cell arrays for repairing defects. The present invention has particular applicability to a semiconductor memory device, more specifically to a static random access memory (SRAM), including a data comparing circuit for a test before shipment.
2. Description of the Background Art
Conventionally, a semiconductor memory, such as a static random access memory (hereinafter referred to as "SRAM") and a dynamic random access memory (hereinafter referred to as "DRAM"), includes a redundant circuit to increase a yield in manufacturing. When any defect exists in a manufactured semiconductor memory, it is repaired through a function of a redundant circuit thereof. More specifically, in a conventional semiconductor memory, a row or a column containing a defective memory cell is functionally replaced with a predetermined spare row or column. Although the present invention is generally applicable to a semiconductor memory, such as an SRAM and a DRAM, the following description explains the case in which the present invention is applied to an SRAM as an example.
FIG. 12 is a block diagram of a conventional SRAM including a redundant circuit. Referring to FIG. 12, an SRAM 100 comprises a memory cell array 80 for storing data, a row decoder 82 responsive to a row address signal RA for selecting a word line WL in the memory cell array 80, a column decoder 83 responsive to a column address signal CA for selecting a column in the memory cell array 80, a write driver circuit 84, and a sense amplifier 85. The SRAM 100 further comprises a spare memory cell column 81 as a redundant circuit, an address programming circuit 86 for programming a defect address indicating a location where a defect exists, and an I/O programming circuit 87.
In operation, the row decoder 82 activates one word line WL in the memory cell array 80 in response to the externally applied row address signal RA. The column decoder 83 selects one column to be accessed in response to the externally applied column address signal CA. More specifically, the column decoder 83 selectively turns on a transmission gate TG1 connected to a column to be accessed so that its bit line can be electrically connected to the write driver 84 or the sense amplifier 85. In writing operation, therefore, an externally applied input data Di is written in the memory cell selected by the row decoder 82 and the column decoder 83. In reading operation, on the other hand, the sense amplifier 85 amplifies a data signal read from the selected memory cell by the row decoder 82 and the column decoder 83 and the amplified signal is provided as an output data Do.
If any defect is found to exist in a certain memory cell column, the defective memory cell column will functionally be replaced with the spare memory cell column 81 as follows. A defect address indicating a location of the defective memory cell column is programmed in the address programming circuit 86 by selectively blowing off a fuse (not shown). The address programming circuit 86 which includes a coincidence detecting circuit, not shown, detects a coincidence of the externally applied column address signal CA and the programmed address signal. A coincidence detecting signal CO is then applied to the I/O programming circuit 87.
A fuse in the I/O programming circuit 87 (not shown) is previously selectively blown off so that a bit line in the spare memory cell column 81 is connected via the transmission gate circuit TG2 to the write driver circuit 84 and/or the sense amplifier 85. As a result, when the column address signal CA coincides with the programmed address signal, access to the spare memory cell column 81 is made in place of normal access to the memory cell array 80. At this time, the transmission gate circuit TG1 is turned off.
While FIG. 12 shows the memory cell array 80 and its peripheral circuits 82, 83 . . . , for the purpose of simplifying the description, a conventional SRAM generally comprises a plurality of memory cell arrays and peripheral circuits thereof. More specifically, while FIG. 12 shows only a block of a memory cell array and its peripheral circuits, a plurality (for example, 64) of blocks are provided in practice.
Since one or two spare memory cell columns (or rows) are provided in each of the memory cell arrays 80 as can be seen from FIG. 12, an SRAM including a plurality (for example, 64) of memory cell arrays contains 64 or 128 spare memory cell columns (or rows).
After an SRAM containing a defect is repaired utilizing a spare memory cell column thereof as described above, the following test before shipment is carried out in a manufacturing factory of semiconductor devices. A test mode signal is first externally applied to the SRAM so that the SRAM can be made to be in a test mode. In the test mode, test data are written into two memory cell arrays within the SRAM. The written test data, namely the two stored data from the two memory cell arrays are then read. The two read data are applied to a comparing circuit to detect whether these data coincide with each other. If the two read data coincide, a defect in the SRAM will be recognized to have been repaired, and if a coincidence is not detected, indicating that the SRAM contains a further detect therein, a further measure will be taken for repairing the defect.
In general, a comparing circuit can compare two data having multi-bits (for example, 8 bits). More specifically, a comparing circuit can detect a coincidence of two read data between corresponding bits thereof. Since one coincidence detecting operation can determine the presence of a defect in a plurality of memory cells, a verification test before shipment can be completed in a short period.
FIG. 13 is a diagram of the transmission gate circuits TG1 and TG2 shown in FIG. 12. Referring to FIG. 13, the transmission gate circuit TG1 is connected between a bit line pair BLa and BLb and a data line pair DLa and DLb in a normal memory cell array, while the transmission gate circuit TG2 is connected between a bit line pair RBLa and RBLb and the data line pair DLa and DLb in a spare memory cell column. The transmission gate circuit TG1 is turned on in response to a column selecting signal of a high level Y.sub.L applied from a column decoder (not shown), so that the bit line pair BLa and BLb and the data line pair DLa and DLb are electrically connected. Although a power supply potential Vcc is applied to a gate of an NMOS transistor 89, thereby turning the transistor 89 on, the column selecting signal Y.sub.L is not affected in potential because of a high on resistance of the transistor 89. Therefore, the column selecting signal of a high level Y.sub.L is correctly applied to the transmission gate circuit TG1 through a fuse 88.
If any defect exists in a memory cell MC1, the fuse 88 is blown off, and the grounded potential is applied via the transistor 89 to the transmission gate circuit TG1 which is then turned off. On the other hand, when a column address signal selecting the column containing memory cell MC1 is applied, a signal of a high level RY is applied via the I/O programming circuit 87 to the transmission gate circuit TG2, which is then turned on. Consequently, the column containing MC1 and the spare memory cell column 81 are functionally replaced.
As described above, a conventional semiconductor memory includes a plurality of memory cell arrays and one or two spare memory cell columns for each memory cell array. Therefore, an SRAM including 64 memory cell arrays, for example, has an ability to repair 64 or 128 defective memory cell columns or rows. In practice, however, not so much repairing ability is necessary because not so many defects can exist in a semiconductor memory experientially. In the aforementioned SRAM, for example, it is experientially recognized that ten or less defects at most can exist. In other words, a conventional semiconductor memory comprises spare memory columns or rows excessively, although unnecessary from the practice point of view, which prevents high integration of a semiconductor memory.
In addition, a conventional spare memory column or row cannot be used for repairing a column or row in other memory cell arrays, for it is provided for each memory cell array. More specifically, when defects exist in more than two memory cell columns or rows, they cannot be repaired, since they cannot be repaired by utilizing one or two spare memory cell columns or rows.